1. Field of the Invention
The invention relates to transforming a high-level design (including functional specifications and functional-level logic such as Boolean expressions, truth tables, and standard macro logic) into hardware implementations, including methods and steps for determining the interconnections and path nets between circuit blocks, circuit components and input/output bonding pads (pins), and the outlining of layout of circuit components, as well as determining and evaluating the performance of the designed circuit components.
2. Background Art
The state-of-the-art in hardware design is to utilize a hardware description language (HDL), such as VHDL or Verilog. To help in debugging, electronic design automation tool vendors provide HDL source browsers that possess a variety of functionalities, such as:    1. Simulation value annotation: where signal values obtained from a simulation database are annotated back to the HDL source.    2. Syntax highlight: where different token types (keywords, comments, identifiers, etc) are highlighted in different colors, fonts, or the like.    3. Semantic navigation: where from a signal usage jump to its declaration or its type declaration, all sources and sinks of the signal are listed, from a VHDL entity jump to its architecture, etc.
VHDL and Verilog grammars also have a “generate” statement. A generate statement can be either conditional (if-generate, case-generate) or iterative (for generate). A conditional generate statement will use a condition to decide whether the enclosed HDL statements will be included in the target design or not. In an iterative generate statement the enclosed statements will be included multiple times depending on the iteration bounds.
Current HDL Source browsers have limited support for dealing with generate statements due to    1. the complexity of evaluating the generate condition or iteration,    2. determining out how to annotate values for signals declared inside the generate statement (multiple copies), and    3. semantic navigation of the design entities declared inside the statements.
Thus, a need exists enabling value annotation and semantic navigation for generate statements through unrolling them.